A dynamic reconfigurable circuit (hereinafter referred to as a reconfigurable circuit) includes a plurality of arithmetic execution units and a network circuit, such that arithmetic instructions and connections between the arithmetic execution units through the network circuit are set in a reconfigurable manner according to configuration data. In a reconfigurable circuit, instructions applied to arithmetic execution units and connections between the arithmetic execution units may be changed (i.e., context switching) during its operation. This allows the arithmetic execution units to be shared in a time-division fashion, thereby reducing the scale of hardware of the entire circuit. Further, a reconfigurable circuit may perform a pipeline operation, and is thus suitable for needs in which a data stream is processed at high speed.
An external buffer memory may be connected to a reconfigurable circuit. Such a buffer may successively store computation results obtained by the reconfigurable circuit and successively supply data to the reconfigurable circuit clock by clock. The provision of an external buffer presents an issue regarding the exchange of data at the time the reconfigurable circuit suspends its computation. A reconfigurable circuit may suspend its computation when a context switching occurs. In such a case, the flip-flops of the reconfigurable circuit are also stopped and unable to load new data. If data is supplied from the external buffer while the computation of the reconfigurable circuit is suspended, the data (i.e., input data) that are supposed to be loaded end up not being loaded.